7th RISC-V Workshop 2017
2017-11-28..2017-11-30
Milpitas, United States
| title | author | length |
|---|---|---|
| 7th RISC V Foundation Update And Workshop Introduction | Rick O'Connor | 12m |
Conference reports 498 registered attendees from 138 companies and 35 universities, with venues repeatedly selling out and 48 talks crammed into 12‑ and… | ||
| RISC V State Of The Union | Krste Asanovic | 43m |
Overview of current RISC-V status and near-term roadmap: the base ISA is base frozen since 2014 and privileged ABI stabilized at 1.10; Linux upstream lands in… | ||
| RISC V Hypervisor Extensions | Andrew Waterman | 13m |
Proposal adds a RISC‑V hypervisor extension that virtualizes supervisor mode by introducing HS/VS/VU modes, exposes background CSRs to hold guest state without… | ||
| Memory Consistency Model Status Update | Daniel Lustig | 23m |
A RISC‑V memory model is released as an RVWMO base model for general software compatibility plus an optional ZTSO extension to expose stricter TSO semantics… | ||
| Keynote: RISC V – Enabling A New Era Of Open Data-Centric Computing Architectures | Martin Fink | 36m |
Western Digital commits to transition one billion cores to RISC‑V across its product portfolio, targets first RISC‑V devices around late 2019–2020, and invests… | ||
| Industrial Strength High Performance RISC V Processors For Energy Efficient Computing | David Ditzel | 24m |
Company emerges from stealth to describe a 7 nm strategy: a 16-core high‑single‑thread “Maxion” Linux SMP plus a tiled array of over 4,000 ET minion cores with… | ||
| Andes Extended RISC V Features | Chuan Hua Chang | 13m |
Andes extends RISC-V with a priority-based preemption CLINT and vectored CLINT that pass interrupt IDs to targets and store 32-bit vector addresses to reach a… | ||
| Customization Of A RISC V Processor To Achieve DSP Performance Gain | Marcela Zachariasova | 09m |
Uses Codasip Studio and a CodAL high-level description to add ISA extensions, run the profiler, and auto-generate SDK, RTL and UVM. Tests compare four configs… | ||
| Freedom U500, A Linux-Capable, 1.5ghz Quad-Core RV64GC Based Soc | Jack Kang | 10m |
Freedom U500 is a Linux-capable RV64GC SoC with a U54 MC core complex (four 64-bit U54 cores plus an S51 management core), running at up to 1.5 GHz, fabricated… | ||
| Revolutionizing RISC V Based Application Design Possibilities With Global Foundries | Gregg Bartlett | 10m |
GlobalFoundries positions its 22FDX process as enabling concrete RISC-V products: 22FDX offering FinFET-level performance at 28nm cost, ultra-low volt… | ||
| RISC V LLVM: Towards A Production-Ready LLVM-Based Toolchain | Alex Bradbury | 24m |
LLVM backend for RISC-V now compiles real code and passes the GCC torture suite 100% for RV32I and RV64I across all opt levels, implements an MC layer… | ||
| A RISC V Java Update: Running Full Java Applications On FPGA-Based RISC V Cores With JikesRVM | Martin Maas | 12m |
A JikesRVM port now runs full Java 6 applications on FPGA-based Rocket cores under Linux, including DaCapo workloads like Lucene and a raytracer, and it passes… | ||
| Microprobe: An Open Source Microbenchmark Generator Ported To The RISC V ISA | Schuyler Eldridge | 14m |
Microprobe is an IBM microbenchmark generator ported to the RISC‑V ISA and intended as open source (pending review). It consumes YAML target definitions and… | ||
| RISC-V Debug Support By Lauterbach TRACE32 | Bob Kupyn | 10m |
Presentation by Bob Kupyn at Lauterbach on November 28, 2017 at the 7th RISC-V Workshop, hosted by Western Digital in Milpitas, California. To view the slides… | ||
| J-Link – Professional Debug Probe Now Available For RISC V | Paul Curtis | 12m |
SEGGER’s J-Link adds RISC-V support (released about a month before the talk) to a family that’s sold over 600,000 units and runs integrated flash programming… | ||
| Porting The ThreadX RTOS To RISC V | John Carbone | 12m |
Express Logic ports ThreadX to RISC-V, implements port to RISC V and verifies it with Spike simulation then on a Microsemi SmartFusion development board… | ||
| xBGAS: A Bridge Proposal For RV128 And HPC | John Leidel | 12m |
Proposes xBGAS, an extended register file and instruction subset that maps RV32/64 binaries into a global object-based address space to address graphs with… | ||
| The Case For Expanding The 16 GPR Standard Beyond RV32E | Mitchell Hayenga | 12m |
Argues for making the 16-GPR option orthogonal to other RISC-V extensions and shows a concrete implementation: modified GCC and G Lipsy toolchains plus the… | ||
| Using Pyrope To Create Transformable RISC V Architectures | Haven Skinner | 11m |
Implements a new HDL Pyrope and a compiler that emits synthesizable Verilog plus a C++ fast emulator, models RISC-V cores as fluid pipelines with elastic… | ||
| Performance Isolation For Multicore Within Labeled RISC V | Zihao Yu | 12m |
Proposes a labeled microarchitecture called arena that conveys software identity to hardware via label registers propagated across cores and caches and… | ||
| A Practical Implementation Of A Platform Level Interrupt Controller (PLIC) | Richard Herveille | 07m |
A fully functional PLIC implementation claims compliance with the RISC‑V spec while introducing dynamic register/memory map generation so the IP auto-builds a… | ||
| RTOS Ports On Microsemi’s RISC V Processor For Iot And Embedded Applications | Nitin Deshpande | 09m |
Presentation by Nitin Deshpande at Microsemi on November 28, 2017 at the 7th RISC-V Workshop, hosted by Western Digital in Milpitas, California. To view the… | ||
| Poster / Demo Previews | Samuel Steffl | 53m |
Poster session collates runnable claims and working demos: an open-source framework that formally verifies RISC‑V cores and emits monitor code used on real… | ||
| Celerity: An Open Source 511 Core RISC V Tiered Accelerator Fabric | Michael Taylor | 24m |
A 16 nm TSMC flip‑chip SOC with ~385M transistors and a 25 mm² die integrates 511 RISC‑V cores split as five Linux Rocket cores, a 496‑core manycore running >1… | ||
| The PULP Cores: A Set Of Open Source Ultra Low Power RISC V Cores For Internet Of Things... | Pasquale Davide Schiavone | 11m |
An open source family of RISC‑V cores targets ultra low power IoT workloads with near‑threshold operation and on‑chip parallelism, multiple taped‑out silicon… | ||
| BOOM v2: An Open Source Out Of Order RISC V Core | Christopher Celio | 22m |
An open‑source out‑of‑order RISC‑V core written in ~16k lines of Chisel is generated inside the Rocket Chip ecosystem, taped out in TSMC 28nm after a… | ||
| Rocket Engines: Low Effort Design Reuse In RISC V Implementations | Pasquale Albert Magyar | 10m |
A new three‑stage core called Bottlerocket reuses RocketChip subcomponents to produce an RV32IMC microcontroller-style CPU with privilege 1.10, SiFive debug… | ||
| Keynote A Perspective On The Role Of Open Source IP In Government Electronic Systems | Linton Salmon | 52m |
DARPA describes concrete efforts to make RISC‑V and open IP practical: claim that custom ASICs give roughly 1000x operations-per-watt over CPUs with an example… | ||
| Boosting RISC V ISA With Open Source Peripherals: An SoC For Low Power Sensors | Elkim Roa | 13m |
Onchip and SiFive release a set of always‑on peripheral IP aimed at battery‑powered sensors and tape out a RISC‑V SoC in 180 nm vanilla logic. Deliverables… | ||
| PicoSoC: How We Created A RISC V Based ASIC Processor Using A Full Open Source Foundry Targeted... | Tim Edwards | 12m |
Full open-source flow produces a RISC-V ASIC targeted to a 180 nm foundry using PicoRV32 and tools Yosys, Vesta, Greywolf, Qrouter, magic, netgen, Icarus and… | ||
| TileLink: A Free And Open Source, High Performance Scalable Cache Coherent Fabric Designed... | Wesley Terpstra | 23m |
An open, reduced-message cache-coherent fabric with formal composition guarantees and a tested on-chip serialization: the protocol implements deadlock-free… | ||
| RISC V Vector Extension Proposal | Roger Espasa | 34m |
Proposes a compact RISC-V vector ISA with 32 vector registers, a configurable VL register that controls how many lanes execute (examples use VL=5)… | ||
| Security Task Group Update And RISC V security Extension | Richard Newell | 14m |
Security group shifts focus to crypto extensions that piggyback on the vector extension, using vector functional units to do wide arithmetic and expose… | ||
| Using Proposed Vector And Crypto Extensions For Fast And Secure Boot | Richard Newell | 14m |
Proposes RISC‑V vector+crypto instructions that implement a AES single‑op block and vectorized GCM and SHA primitives, with assembly that strip‑mines the same… | ||
| Using RISC V As a Security Processor For DARPA CHIPS And Commercial IoT | Mark Beal | 13m |
RISC-V is used as a tiny dedicated security processor that mediates access to crypto accelerators and holds secrets off the main CPU the design integrates AES… | ||
| ISA Formal Task Group Update | Rishiyur Nikhil | 12m |
A machine-readable formal ISA specification is written in a simple functional notation using a Haskell syntax subset, with an algebraic AST, a 32-bit decode… | ||
| Strong Formal Verification For RISC V: From Instruction Set Manual To RTL | Adam Chlipala | 24m |
Claims a full machine-checked refinement from the RISC‑V ISA to RTL using a Coq proof assistant guided framework and a Bluespec-like language that compiles to… | ||
| GRVI Phalanx Update: Plowing The Cloud With Thousands Of RISC V Chickens | Jan Gray | 12m |
A reconfigurable overlay of simple RISC-V cores and a hoplite NoC runs as an FPGA accelerator fabric and compiles C++/GCC kernels into many-core jobs without… | ||
| A Tightly Coupled Light Weight Neural Network Processing Units With RISC V Core | Lei Zhang | 09m |
A tightly coupled neural accelerator integrates with a Rocket RISC‑V core via custom RISC‑V coprocessor instructions and a shared L1/cache interface and… | ||
| A RISC V Based Linear Algebra Accelerator For SoC Designs | Samuel Steffl | 15m |
Describes the LA core: a RISC-V extension with 68-instruction RISC-V extension that adds a dual-precision systolic LA exec unit, four configurable LA mem… | ||
| Packet Manipulator Processor A RISC V VLIW Core For Networking Applications | Salvatore Pontarelli | 11m |
Claims a RISC‑V VLIW RISC-V core built as a packet processor that implements parsing, routing, ACLs and custom tunneling in hardware‑accelerated pipelines… | ||
| Adding A Binarized CNN Accelerator To RISC V For Person Detection | Guy Lemieux | 13m |
A person detector runs on a tiny FPGA board with ~1 Mbit SRAM and a VGA camera downscaled to 32×32 pixels, using an Orca RISC‑V core plus binary CNN… | ||
| RISC5: Improving Support For RISC-V In Gem5 | Alec Roelke | 10m |
Adds full RV64I + IMAFDC support to gem5, implementing integer, multiply, atomic, floating-point and compressed instruction handling and a decoder that copes… | ||
| Renode: A Flexible, Open Source Simulation Framework For Building Scalable, Well Tested... | Michael Gielda | 11m |
Renode is an open source simulator that emulates full SoCs so teams run production binaries without a separate simulator build and simulate multiple nodes in… | ||
| QEMU Based Hardware Modeling Of A Multi Hart RISC V Based FPGA With Execution Contexts Free... | Daire McNamara | 11m |
Implements QEMU extensions to model a five-core RISC‑V FPGA SoC so one E51 core boots as a privileged manager and enforces isolation while other cores run… | ||
| FireSim: Cycle Accurate Rack Scale System Simulation Using FPGAs In The Public Cloud | Sagar Karandikar | 24m |
FireSim compiles Chisel/RTL into FPGA simulators on EC2 F1, packs four Rocket cores per FPGA to yield 128 simulated cores per F1, and runs rack-scale… | ||
| 7th RISC V Workshop Wrap | Rick O'Connor | 04m |
All slides and videos get posted on riscv.org next week, raw footage undergoes post-processing first; members find a PDF agenda for tomorrow’s Board, Technical… | ||
| RISC-V Western Digital Thank You | 01m | |
Western Digital hosts the 7th RISC-V Workshop at the original SanDisk facility, with the local team handling logistics, setup and last-minute fixes so sessions… | ||
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