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Alex Bradbury

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titleconferencedate
Improvements to RISC-V Vector code generation in LLVMRISC-V Summit Europe 20252025-05-12
LLVM adds middle-end and backend changes for RVV including VL tail folding and non-power-of-two SLP support, a pass to reduce VL to demanded, and backend…
Talk on
RISC-V LLVM State of the UnionRISC-V Summit North America 20242024-10-22
Status update on RISC-V LLVM: LLVM supports the mandatory RV64G/23 extensions, has growing contributor diversity, and runs a CI-backed test farm using QEMU…
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Production ready RISC V Support in LLVM Clang 9RISC-V Summit 20192019-12-09
LLVM/Clang now includes production-grade RISC-V support as a default target in Clang 9, covering RV32I and RV64I with MAFDC and all ABIs except the embedded E…
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Open source hardware licensing: a lowRISC experience reportWeek of Open Source Hardware 20192019-06-13
lowRISC reports sticking to upstream licenses (original Rocket was BSD then Apache) and now releases new IP under Apache 2.0, uses CC‑BY for documentation, and…
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Panel Discussion: Open Source LicensingWeek of Open Source Hardware 20192019-06-13
Panel debates concrete tensions: license text ambiguity forces legal interpretation and risks incompatible OHL variants when projects try to redefine scope…
Panel on
LLVM for RISCV8th RISC-V Workshop Barcelona 20182018-05-07
Describes adding bit-manipulation ops to the LLVM RISC-V backend with working RV32 and RV64 support now upstream, claiming parity with GCC for code size on the…
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Poster / Demo Previews8th RISC-V Workshop Barcelona 20182018-05-07
Poster session previews list concrete results and demos to see: a quantum‑resistant secure boot shows large speedups on HiFive hardware; CGEN generates…
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RISC V LLVM: Towards A Production-Ready LLVM-Based Toolchain7th RISC-V Workshop 20172017-11-28
LLVM backend for RISC-V now compiles real code and passes the GCC torture suite 100% for RV32I and RV64I across all opt levels, implements an MC layer…
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