Poster / Demo Previews
summary
Poster session previews list concrete results and demos to see: a quantum‑resistant secure boot shows large speedups on HiFive hardware; CGEN generates assemblers, disassemblers and an ISO‑complete compliance test suite from one architecture description; a dynamic information‑flow tagging implementation for a PULP RISC‑V core adds protection with negligible area and latency overhead; Google verification using Sting finds 30+ RTL and toolchain issues; Taiga FPGA softcore reports up to 28% IPC uplift from early commit; live demos include simulator‑to‑HDL cosimulation, hot‑plug CPU flow, and memory‑side acceleration that can beat caches for specific kernels.
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chapters (37)
- 0:00Workshop introduction
- 0:43Quantum-resistant security
- 1:30Toolchain architecture
- 2:46Dynamic security protection
- 4:33Customizable processor cores
- 6:56Open source hardware growth
- 7:44Instruction cache optimization
- 10:28Verification using STING
- 11:21Hardware-software simulation
- 12:23Approximate computing
- 13:48Java on RISC-V
- 15:28Power-aware SoC platform
- 17:32Configurable IP portfolio
- 19:13Floating-point verification
- 20:32Microprocessor testing
- 22:12Open source RTL ecosystem
- 25:14Rust on RISC-V
- 27:30Memory protection units
- 30:04Out-of-order soft processor
- 32:54Super-optimization framework
- 34:55Hardware-assisted scheduling
- 37:06Microcontroller reconfigurability
- 39:16Chisel educational initiatives
- 41:53CPU hot-plugging
- 44:16Vetrix and STING update
- 45:45JVM and JIT synthesis
- 48:04Embedded systems support
- 49:53Side-channel protection
- 52:05Hardware security enforcement
- 54:32Memory-centric optimization
- 57:25SDK for SR5 CPUs
- 59:10Security in storage devices
- 1:01:10Formal verification framework
- 1:02:23Demo table overview
- 1:03:39High-speed simulation
- 1:07:33Multi-node simulation
- 1:09:07Advanced system debugging
