The Hybrid Threading Processor for Sparse Data Kernels
summary
A RISC‑V based RV64G core array with custom thread and message instructions implements a high‑thread barrel processor that pauses threads waiting on memory and runs event‑driven scheduling, small per‑thread caches (≈55–256 B), software coherence and atomics at memory. Simulation uses cycle‑accurate functional timing plus GlobalFoundries power models and a memory‑side cache with GDDR6 16‑byte returns. Best results use 1024 threads, 1.2 GHz cores and 8–16 byte accesses, yielding roughly 24x energy efficiency on a sparse spectral clustering kernel versus reference platforms.
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chapters (12)
- 0:00Introduction and motivation
- 1:50Hybrid threading concept
- 3:12Event-driven processor design
- 6:42System architecture overview
- 8:28Chiplet-based modeling
- 9:32Application: Spectral clustering
- 10:14Sensitivity analysis results
- 12:44Thread execution visualization
- 14:30Performance vs reference platforms
- 15:51Conclusion and future outlook
- 16:12Q&A: Synchronization methods
- 17:17Q&A: Memory access width
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