Debug Specification
summary
A RISC‑V debug specification defines a debug module with mandatory abstract commands to read/write GPRs, optional FPR/CSR access, an optional program buffer (0–32 words) for debugger‑loaded code, and a heart selection scheme supporting up to heart ID up to 2^20 with halt/resume flow via DMCONTROL and DCSR. Implementations include OpenOCD, Spike and SiFive Rocket support; system bus access, triggers (virtual address/data match) and quick access are optional. The spec is draft and not yet ratified.
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chapters (11)
- 0:00Introduction to debug spec
- 1:06History of debug working group
- 3:35Why debug spec is needed
- 6:46Debug spec overview and features
- 11:45Debug module and heart interface
- 17:10Selecting and controlling hearts
- 20:50Abstract commands and program buffer
- 24:03Single stepping and triggers
- 25:52System bus mastering and quick access
- 29:06Public implementations and ecosystem
- 30:53Current state and future tasks
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