Vector ISA Proposal Update
summary
Register-type encoding moves out to an optional extension and the base uses a more classical opcode-driven type scheme; register-type extension moved to an extension. Scalar support survives via a one-element vector load and a splat that ignores VL, and the mask encoding shrinks to one bit (LSB of v0). Four load/store classes (unit, strided, gather, scatter with unordered), mandatory FP16 support (FP16 mandated), wiring multiplies with a 17-bit trick, popcount/first-set mask helpers, slide up/down and full register permute are all specified and the design aims to fit into existing major-op opcode space.
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chapters (13)
- 0:00Intro
- 0:49Updates & Discussion points
- 2:09Register types pushed to extension
- 4:17Scalar support
- 5:49Masked execution
- 9:43Vector Memory Instructions
- 11:44Vector Integer Instructions
- 13:18Fixed Point Support: vclip
- 14:15Vector Floating Point Instructions, w/ FP16 operation instructions
- 14:50Vector Floating Point Multiply Add
- 15:38Vector Convert From Integer to Float
- 21:20Vector Mask Operations
- 23:15Vector Reductions
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