Roger Espasa
where else to find them
no profile links on file
what they talk about
where they keep going back
- RISC-V Summit North America2 editions2023–2024
all 7 in the filters
on a stage with
- Alberto Morenoonce
- Alessandro Camposonce
- Calista Redmondonce
all 6 in the filters
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit | RISC-V Summit North America 2024 | 2024-10-22 |
Semidynamics runs Llama‑2 7B FP16 via ONNX Runtime on an R5‑controlled chip that integrates core, Vector and Tensor units with no external DMA. The Tensor unit… | ||
| Keynote Panel: Powering Local Innovation and Global Success with RISC-V | RISC-V Summit North America 2024 | 2024-10-22 |
Panel argues that RISC-V moves from experiments to deployed systems: a NASA public‑private program selects an eight-core RISC-V vector processor for the High… | ||
| Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions | RISC-V at embedded world 2024 | 2024-04-09 |
Proposal: a single RISC‑V element combining an out‑of‑order Atrio R5 core, an out‑of‑order vector unit supporting RVV 1.0 and a configurable tensor unit… | ||
| Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instr... | RISC-V Summit North America 2023 | 2023-11-06 |
Semidynamics extends the RISC-V Vector Extension with three custom tensor instructions that operate directly on the vector register file (no extra state… | ||
| Semidynamics Highly Configurable OOO Vector Unit | RISC-V Summit Europe 2023 | 2023-06-05 |
Fully RVV1.0 compliant and offered in configurable sizes (start at 4, options up to 32 vector cores), the unit runs fully out-of-order vector renaming with… | ||
| OVI: The Open Vector Interface | RISC-V Forum: Vector & Machine Learning 2021 | 2021-09-15 |
OVI is an open protocol that wires a RISC‑V core to a loosely coupled vector unit and is already used to connect the Avispado core to the Vitruvius VPU and… | ||
| Semidynamics New Family of High Bandwidth Vector-Capable Cores | RISC-V Global Forum 2020 | 2020-09-03 |
SemiDynamics unveils two RISC‑V cores: Avispado 220, a two‑wide in‑order core that sustains 64+ outstanding misses past L1 and implements RVV 1.0 support, and… | ||
| Vector ISA | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
RISC-V adds 32 vector registers V0–V31, a programmable VL register that limits active elements, and a V-config that selects register count and element width… | ||
| Vector ISA Proposal Update | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Register-type encoding moves out to an optional extension and the base uses a more classical opcode-driven type scheme; register-type extension moved to an… | ||
| RISC V Vector Extension Proposal | 7th RISC-V Workshop 2017 | 2017-11-28 |
Proposes a compact RISC-V vector ISA with 32 vector registers, a configurable VL register that controls how many lanes execute (examples use VL=5)… | ||
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