RISC V Vector Extension Proposal

on YouTube ↗34m

" summary

Proposes a compact RISC-V vector ISA with 32 vector registers, a configurable VL register that controls how many lanes execute (examples use VL=5), per-register element types and three shapes (scalar/vector/matrix), strided loads, indexed gather/scatter, vector atomics, and a single convert opcode. Implementation mandates zeroing of inactive elements to allow out-of-order designs, stores write only VL elements, memory ordering follows loop semantics, and Esperanto reports an early RTL prototype.

AI-written summary · about

" chapters (21)

1. 0:00Introduction and motivation
2. 1:23Vector ISA features and benefits
3. 2:25Registers and vector state
4. 3:53Vector instruction set basics
5. 5:41Simple vector add example
6. 7:03SIMD vs vector execution
7. 8:49Scalar operations in vectors
8. 10:33Masked execution explained
9. 12:37Vector memory loads
10. 14:42Indexed vector loads
11. 16:05Vector memory stores
12. 17:08Memory ordering guarantees
13. 18:32Typed vector registers
14. 22:07Variable vector length support
15. 23:10Register file organization
16. 27:05Software usage and set VL
17. 28:29Encoding and instruction format
18. 29:11Exceptions and future plans
19. 30:35Speaker’s vector ISA history
20. 31:38Software support and next steps
21. 32:44Q&A on page faults

" related talks

• 13mUnleashing ML Processing Power Through RISC-V Vectors: Applications, Implementation and...B. Barker · RISC-V Summit North America 2025
• 01h 45mPorting SIMD to RISC-V VectorsDaniel Thompson · RISC-V Summit Europe 2026 Developer Workshops
• 01h 45mPorting SIMD to RISC-V Vectors | Corrected AudioDaniel Thompson · RISC-V Summit Europe 2026 Developer Workshops
• 11mSimulate, trace, and evaluate a RISC-V system leveraging very long vectorsPablo Vizcaino · RISC-V Summit Europe 2024
• 12mDemo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor InstructionsJosé María Arnau · RISC-V Summit North America 2023
• 24mMoving to RISC-V Vector: A Practical Journey of AI Operator OptimizationGuodong Xu · RISC-V Summit North America 2025
• 23mSemidynamics New Family of High Bandwidth Vector-Capable CoresRoger Espasa · RISC-V Global Forum 2020
• 22mMatrix Extensions for RISC-VDelivering on the PromisePhilipp Tomsich · RISC-V Summit Europe 2026