A RISC V Java Update: Running Full Java Applications On FPGA-Based RISC V Cores With JikesRVM
summary
A JikesRVM port now runs full Java 6 applications on FPGA-based Rocket cores under Linux, including DaCapo workloads like Lucene and a raytracer, and it passes the VM’s core test suite; the baseline non-optimizing JIT is complete while the optimizing compiler is work in progress. The FPGA setup executes over a trillion instructions so researchers can evaluate long-running Java behavior, prototype a GC coprocessor, and collect per-allocation traces to reveal DRAM miss spikes during garbage collection.
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chapters (17)
- 0:00Intro
- 0:16Managed Languages
- 0:35Java on RISC-V
- 1:11Talk Outline
- 2:23Porting The Jikes Research VM CARRV-2017 Workshop Paper
- 3:07FPGA Performance Results
- 3:39PART II 1. Running JikesRVM on Rocket Chip
- 3:50Wake Up and Smell the Coffee
- 4:21Managed Language Challenges
- 4:47Limitations of Simulators
- 6:40Hardware Software Co-Design
- 7:07Motivating Example
- 8:13Memory Allocation Latency
- 9:01DRAM Row Misses
- 9:51PART III 1. Running JikesRVM on Rocket Chip
- 10:09JVM on RISC-V Progress
- 11:11Announcement
