Celerity: An Open Source 511 Core RISC V Tiered Accelerator Fabric
summary
A 16 nm TSMC flip‑chip SOC with ~385M transistors and a 25 mm² die integrates 511 RISC‑V cores split as five Linux Rocket cores, a 496‑core manycore running >1 GHz, plus ten low‑voltage cores; Rocket/accelerator clock at 625 MHz and IO at 400 MHz. On‑chip SRAM backs a binarized neural network accelerator fed by manycore stores; HLS generates the NN, BaseJump provides the basejump STL IP, FPGA bridge, boards and sockets, and the whole design and firmware are released open source.
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chapters (5)
- 0:00Introduction and overview
- 6:23Many-core design details
- 15:11BaseJump ecosystem
- 20:52Open-source hardware flow
- 21:34Q&A and closing
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