Poster / Demo Previews
summary
Poster session collates runnable claims and working demos: an open-source framework that formally verifies RISC‑V cores and emits monitor code used on real processors; a MicroPython port to RISC‑V; a PolarFire demo showing secure boot and a dual‑core lockstep with a two‑cycle skew for fault detection; an FPGA CNN accelerator reporting 73× speedup (≈1.75 GHz equivalent) in <5,000 LUTs at 24 MHz; anomaly detector achieving >99% TPR and <1% FPR on advanced side‑channel attacks.
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chapters (6)
- 0:00Poster
- 42:01Compliance Task Group
- 44:35Software Task Group
- 46:39Books
- 50:07Vectra
- 51:27Formal Verification
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