Using RISC V As a Security Processor For DARPA CHIPS And Commercial IoT
summary
RISC-V is used as a tiny dedicated security processor that mediates access to crypto accelerators and holds secrets off the main CPU the design integrates AES SHA and ECC engines plus TRNG and a root of trust and exposes a simple API to the host The processor is RV32I+ and is about 20k–25k gates with accelerators running in parallel Secret handling is enforced by machine-mode ROM / signed user-mode RAM and the kit delivers AES SHA ECC accelerators and authenticated firmware for easy drop-in reuse at under 1% area cost
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chapters (9)
- 0:00Introduction and motivation
- 1:07RISC-V in security subsystems
- 2:33Crypto subsystem architecture
- 4:23Previous integration challenges
- 5:50Benefits of separate RISC-V core
- 7:15Security processor implementation
- 9:21Partitioning and supply chain
- 10:47Zephyr OS integration example
- 11:52Verification and API benefits
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