An Open Source Approach to System Security
summary
RISC‑V moves from secrecy to open specs that accelerate review and tool development, with 69 listed cores and a projection of ~64 billion chips by 2024. Work includes AES and SHA-1 accelerators and vector/scalar instructions for RSA and tiny embedded crypto, plus physical memory protection (PMP) and privileged modes. Formal projects deliver a spec language and tools called BestBin and Grift and publish a secure voting machine prototype (hardware and software) for public analysis.
AI-written summary · about
chapters (9)
- 0:00Start
- 2:46start from a clean slate
- 3:19defines four different privilege modes
- 6:49implement public key cryptography
- 7:19run the software faster on those tiny little platforms
- 9:01propose a secure monitor architecture
- 11:20working on a secure mcu protection profile
- 12:39define the security properties for your platform
- 15:57deal with open source versus confidential proprietary implementation
related talks
13mRISC-V: Securing the Future of Open Source Computing
21mRISC-V International Security Overview
16mKeynote: RISC-V Security - Current Initiatives and Future Trends
47mA Security RISC? The State of Microarchitectural Attacks on RISC-V
20mRISC-V open designs and contributions to hardware security research and development activities
45mThe Future of Security is in Open Silicon
13mUsing RISC V As a Security Processor For DARPA CHIPS And Commercial IoT
52mEnabling New Security Frontiers: Deep-Dive Into Implementing Confidential Computing on RISC-V