Developing with FreeRTOS and RISC V
summary
FreeRTOS is shown running on RISC-V with both GCC and IAR toolchains and board-specific ports (Vega/SiFive examples), proving the kernel’s extensibility: chip‑specific headers let the context switch save and restore six additional registers and plug into the CLINT trap handler. Options include reusing main stack as the interrupt stack to save RAM or allocating a static interrupt stack. A live test suite boots on the board and signals success by an LED flashing every 3 seconds; pausing the test triggers an assertion and the blink pattern stops.
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chapters (5)
- 0:00Introduction to FreeRTOS
- 5:49Source code and porting
- 10:14Customizing the kernel
- 15:04Interrupts and memory
- 19:31Live demo and conclusion
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