GNU CGEN for RISC V Tool Chain Customization

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" summary

Demo shows GNU CGEN generates libopcodes and libinsn to produce assembler, disassembler and a table‑driven simulator integrated with GDB and aims for a 24‑hour turnaround from instruction spec to toolchain. It supports RV32 and RV64 with per‑machine ISAs, works around a word‑size bug by generating two sets of files, and implements the proposed bit‑manip extension — B subextension implemented in 7 days — patches for simulator/GDB are under review though regression tests remain manual.

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" chapters (41)

1. 0:00Intro
2. 1:19Preparatory Material
3. 1:57Structure of This Tutorial • A short introduction to CGEN
4. 3:00What is CGEN?
5. 4:20Where CGEN fits
6. 5:46A Hardware View of the World
7. 6:29A Software View of the World
8. 7:20General CGEN Entites
9. 8:48Architecture and ISAS
10. 9:57Defining the Hardware Hierarchy
11. 11:43Low Level Hardware: Registers
12. 13:49The ISA: Instruction Fields and Operands
13. 15:46The ISA: Instructions
14. 18:03The Key Files cpu/riscv.cpu
15. 20:24Configuring the Build System opcodes/configure ac
16. 20:55Code Changes opcodes/disassemble.c
17. 21:27Configure and Build $ mkdir bd
18. 22:27Mandatory Components
19. 23:50Configure and Build the GNU Assembler
20. 24:21Extending cpu/riscv.cpu
21. 25:02Semantic Information
22. 26:15Hand-written: riscv.c
23. 29:14Hand-written: sim-main.h
24. 29:46Simulator Configuration
25. 30:36Configure, Build and Run Under GDB
26. 31:13Preprocessor Macros Function macros
27. 32:14Macro Example from RISC-V
28. 33:03Multiple ISAs for Assembler/Disassembler
29. 34:44Multiple ISAs for the Simulator Define a new much for 32-bit RISC-V Define a new CPU for 32-bit RISC-V
30. 35:05Multiple ISAs for the Simulator: A Problem Problem: CPUs have to have the same word-bitsize
31. 35:28sim/riscv/Makefile.in: Split arch Rule
32. 35:53sim/riscv/Makefile.in: Split cpu Rule
33. 36:47sim/riscv/Makefile.in: Using XLEN
34. 38:18Multiple Disassembler/Assembler Extensions
35. 40:49Multiple Simulator Extensions
36. 42:25Pseudo Assembler Instructions
37. 44:29RVEXT Attribute for Bitmanip
38. 44:41RVEXT Macros for Bitmanip
39. 44:53Add Generic B Supporting Machs
40. 45:20Enumerate 'B' Instructions with Semantics
41. 46:26Current Status and Issues: CGEN • CGEN is now in git

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