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Scalable, Configurable Neural Network Accelerator Based on RISC V Core

Talkat RISC-V Summit 2019 · 2019-12-09..12-12· [machine-learning]
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slides:none on file

LG Neural Engine (LNE) is a configurable NN accelerator built around a RISC-V Rocket core (4‑stage RV32I, M/C optional) plus a tiled NPU, silicon proven on TSMC 28nm HPC+. Architecture scales to 128 cores (tiles of NPUs), each tile hosting on‑chip man‑blobs and a shared TSM, with a data‑movement engine (DMA) supporting 2D/3D layouts, multicast/broadcast and AXI host interfaces. NPU datapath runs 16‑bit (8x8) and 8‑bit (16x16) MAC arrays, offers binarized weights for higher FPS, and targets 1 GHz operation.

AI-written summary · about

  1. 0:00Introduction
  2. 0:34LG Neural Engine
  3. 0:52LNE's Features
  4. 2:00LNE's Architecture
  5. 3:47Neural Processing Unit (NPU)
  6. 4:32Common iCache/Data Memory
  7. 4:55MBLOBs and TSM
  8. 5:28Data Movement Engine (DME)
  9. 6:05Host Access
  10. 6:28Ring Bus
  11. 7:28LNE's Software Flow
  12. 7:49Demo
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