The SiFive Vector Processor
summary
SiFive describes a vector roadmap centered on a configured VI2 series core with a 32 register file and 512 bit physical vector registers that software can extend to 4096 bits and that implements a 128-bit data path completing a 512-bit register in four cycles. A vector evaluation platform ships now with GCC intrinsics, Spike and a performance model, DSP and FFT kernels, and measured gains like a >22x speed-up on 16×16 float32 matrix multiply versus scalar code.
AI-written summary · about
chapters (10)
- 0:00Intro
- 0:42RISCV Vector Extensions
- 2:46SiFive Vector Processor
- 4:35Roadmap
- 5:17VI2 Series Core
- 8:27Performance
- 9:53Matrix multiplies
- 11:38Vector Evaluation Platform
- 13:49Vector Intrinsics
- 14:29Summary
related talks
39mKeynote: European Processor Initiative & RISC-V
14mKeynote: Welcome & Opening Remarks
27mComputers for Super-Human AI
17mKeynote: RISC-V Outperforming Expectations
14mI Fought the Law and the Law Lost: Moore’s Law, Dennard Scaling & RISC-V
21mKeynote: EPI, The European Approach for Exascale Ages. The Road Toward Sovereignty
14mFoundational HPC Systems for 2020 and Beyond
21mEnabling the next level of scientific exploration