Open Source Verification Platform for RISC V Processors

on YouTube ↗23m

" summary

An open-source RISC-V verification platform generates constrained-random instruction streams, produces page tables, trap handlers and traces, and plugs into ISSs and simulators (spike, OVP, VCS, Incisive, Veloce) to compare RTL vs ISS results. A handshake for debug mode verifies saving/restoring context, a CSV trace enables a portable functional-coverage model, and application to the ibex core case study finds memory, CXRs and illegal-instruction issues. Generator performance improves 5× speedup and the project moves to CHIPS Alliance.

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" chapters (11)

1. 0:00Introduction to open-source RISC-V verification
2. 1:04UVM-based instruction generator overview
3. 3:11Illegal instruction and memory mapping support
4. 4:34Debug mode verification with handshake
5. 7:17Functional coverage model explained
6. 9:50Performance optimizations for test generation
7. 10:53End-to-end verification flow architecture
8. 14:41Case study on Ibex core verification
9. 16:25Future roadmap and extensions
10. 19:31Configuration and ecosystem setup
11. 20:35Transition to CHIPS Alliance and Q&A

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