Tutorial: Choosing Appropriate Verification Techniques for Desired RISC...

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" summary

A structured verification flow centers on an Imperas reference model plus a standardized RISC-V Verification Interface (RVVI) with rvvi trace and an rvvi API that support configurable extensions, multi-hart and multi-issue cores. Flows compared are post-sim trace-compare, self-checking signatures and runtime step-and-compare; a demo runs a Hello World, performs over 3 million comparisons, flags a PC mismatch and an X9 register divergence, and finds an asynchronous interrupt-priority bug resolved by a prediction engine.

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" chapters (11)

1. 0:00Intro
2. 0:38RISC-V Design Verification challenges
3. 1:38Post-simulation trace file compare
4. 5:52Trace compare: Process
5. 7:57Signature comparison
6. 9:07Processor reference model
7. 11:48Async step and compare: Pros and Cons
8. 24:10Asynchronous events
9. 32:32Verification planning
10. 40:03DUT considerations affecting verification method
11. 41:24Technology considerations affecting verification method

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