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Tutorial: Side-Channel Attacks and Transient Execution Vulnerab...

Talkat RISC-V Summit 2022 · 2022-12-13..12-14· [security]
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Covers concrete side channels (power, EM, timing, cache, TLB, DRAM rowhammer) and shows how transient execution leaks secrets by creating microarchitectural state that survives until retirement, enabling Meltdown-style cache exfiltration and Spectre-style predictor mistraining. Describes defenses that actually work versus costly mitigations: avoid creating microarchitectural state for faulting loads, Spec Terminator: 2.6% cache penalty, 6% for all variants, and verification tools used by silicon vendors. Presents RISC-V CFI options with tradeoffs: shadow stacks and execute-only memory, memory tagging, pointer authentication, landing‑pad labels, and measured performance/memory costs.

AI-written summary · about

  1. 0:00Introduction to tutorial
  2. 0:41Side vs covert channel attacks
  3. 2:23Physical side-channel basics
  4. 7:00Microarchitectural vs physical channels
  5. 8:47Cache timing side-channel attacks
  6. 11:58Rowhammer bit-flip attacks
  7. 12:59Transient execution overview
  8. 16:09Meltdown vulnerability details
  9. 19:18Spectre attack mechanisms
  10. 22:05Spectre countermeasures and costs
  11. 23:54Spectre amplification attacks
  12. 25:19Security verification tools pitch
  13. 26:33Rowhammer explanation
  14. 27:57Control Flow Integrity intro
  15. 29:22Memory corruption vulnerabilities
  16. 31:51Code reuse attacks explained
  17. 33:39Traditional defense mechanisms
  18. 36:35Heuristic detection techniques
  19. 40:08Detection-based defenses
  20. 41:53Memory tagging limitations
  21. 43:39Pointer authentication overview
  22. 45:29Dynamic information flow tracking
  23. 47:15Pointer bounds protection
  24. 49:02Execute-only memory technique
  25. 51:15Shadow stacks explained
  26. 53:24Control Flow Integrity proposals
  27. 56:56CFI granularity comparison
  28. 59:50CFI benefits and drawbacks
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