Redefining the Embedded Development Landscape with Software-defined SoCs
summary
XMOS presents a RISC-V–compatible, multi-core software-defined SoC that maps deterministic hard-real-time tasks to dedicated hardware threads and stripes soft-real-time applications across other threads under an RTOS. Devices run 500–800 MHz, scale linearly by tiling chips, and claim to cut the traditional $50–100M, multi-year SoC effort to software-driven development. Demonstrated systems include a voice pipeline, a mass-market license-plate reader shipping next year, and a multi-axis motor controller; timing guarantees rely on single-digit nanosecond resolution and spatial partitioning.
AI-written summary · about
chapters (16)
- 0:00Introduction
- 0:30XMOS
- 1:14Motivation
- 2:11Traditional approaches
- 3:19XMOS mission
- 3:47XCore
- 5:19Portfolio
- 7:07Integration and differentiation
- 8:00Software and tools
- 9:13Multicore motivation
- 10:39Architecture
- 12:20System Architecture
- 14:17License Plate Recognition
- 14:46Motor Controller
- 15:14Robotics
- 15:53Summary
related talks
11mDriving SoC Innovation with Synopsys RISC-V Solutions
25mOpen Source Software Stack for Heterogenous embedded devices
32mHeterogeneous Linux and RTOS Software Architecture for Low-Price RISC-V...
43mRISC-V CPU Project in Western Digital
20mVirtual Prototypes and Open Source Hardware Design in Research and Education
15mRISC-V CPUs for the New Era of Heterogeneous Computing
18mRISC-V Performance Delivered
11mDemo: Accelerating SW Development and Validation of RISC-V Based Designs