Virtual Prototypes and Open Source Hardware Design in Research and Education
summary
Open source RISC-V virtual prototype implemented in SystemC TLM 2.0 runs full OSes and claims 10x–100x faster than RTL for early software development; a configurable core generates Verilog via SpinalHDL, synthesizes to FPGA (HX8K) at ~20 MHz in SoC mode and ~43 MHz for the core, using 26–44% of the FPGA, and was mapped to a commercial 28 nm node. Features include a virtual breadboard with Lua models, FPGA hardware-in-the-loop bridges, and symbolic execution for finding OS bugs.
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chapters (14)
- 0:00Virtual prototypes & open source HW
- 1:04Virtual prototyping in SOC design
- 2:07System-level virtual prototypes
- 3:52RISC-V virtual prototype details
- 5:15Interactive HW simulation
- 5:58Hardware-in-the-loop prototyping
- 7:01Virtual prototype to RTL with SpinalHDL
- 8:25Symbolic execution for embedded systems
- 10:51Symbolic execution results
- 11:34Research & education benefits
- 12:41Q&A on modeling & scripting
- 16:14PCB & bus simulation use case
- 16:58SystemC virtual prototypes & FPGAs
- 19:49Closing remarks
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