Early performance estimation using virtual prototypes and open-source SW

on YouTube ↗20m

" summary

Virtual prototypes based on SystemC TLM2 run full software stacks far faster than RTL sims and yield early architectural latency and bandwidth numbers. An open-source stack centered on DVT-Rise produces an ISS for RISC‑V, composable peripheral models and common bus interfaces, with a Python front end (PisaC/PiCC) for structural composition. Trace formats feed an open tool called SC viewer for transaction waveforms and CSV post‑processing, enabling dashboards that aggregate latency, bandwidth and min/max statistics.

AI-written summary · about

" chapters (12)

1. 0:00Virtual prototyping intro
2. 1:06Hardware-software gap in SoC
3. 2:55Early software visibility
4. 4:00DVT-Rise ISS
5. 6:30Modeling peripherals
6. 8:36SCC peripheral library
7. 10:05SystemC loosely timed
8. 11:29Python with PiSC
9. 12:54Simulation results importance
10. 14:22SC Viewer analysis
11. 16:30Unified performance dashboards
12. 17:33Q&A

" related talks

• 13mEarly RISC-V Software Verification with SIM-VLukas Jünger · embedded world 2023
• 09mExploring RISC-V architectures with VPSim, a virtual prototyping environmentLilia Zaourar · RISC-V Summit Europe 2024
• 17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...Larry Lapides · RISC-V Summit 2022
• 14mDemo: More Than Point Tools: RISC-V SolutionsLarry Lapides · RISC-V Summit North America 2025
• 15mAccelerating SDV with Synopsys Virtual Prototyping and Silicon Lifecycle ManagementStewart Williams, Marc Serughetti, Pawini Mahajan · SOAFEE Virtual Symposium 2022
• 10mRISC-V Virtual Platforms for Early RISC-V Embedded Software DevelopmentKevin McDermott, Lee Moore, Hugh O’Keeffe · 8th RISC-V Workshop Barcelona 2018
• 11mDemo: Accelerating SW Development and Validation of RISC-V Based DesignsKamal Desai · RISC-V Summit North America 2023
• 14mAccelerate RISC-V DSA design with Virtual Board BuilderHualin Wu · RISC-V Summit Europe 2024