SystemRDL and PeakRDL
summary
SystemRDL is an Accellera open standard for register maps that already has a stable Python compiler on the SystemRDL GitHub and a suite of importer/exporter tools. From a single RDL source it generates VHDL, SystemVerilog, UVM, IP-XACT, HTML, markdown, C headers, C++, Python and a WIP SVD; it supports hierarchical reuse and enums and decodes/encodes fields. A SpinalHDL Regif interface generates SystemRDL and the reverse, enabling mixed-core workflows.
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