SpinalHDL: Software generated hardware
summary
SpinalHDL is a Scala-based DSL that emits synthesizable VHDL/Verilog netlists and runs as ordinary Scala code, not a separate compiler. It enforces explicit RTL (no hidden magic), performs lint-like checks, and converts software data structures into hardware — example: a memory-mapper tool that takes a Scala map of address actions and generates multiplexers and assigns. The ecosystem includes VexRiscv 5-stage RV32 CPU (optional C extension, mul, data cache) proven on FPGAs at roughly 340 MHz.
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chapters (11)
- 0:00Intro
- 0:45Hardware Description API
- 2:39Hardware API
- 5:03Simple example
- 13:19Boost
- 15:07MemoryMapper
- 16:51VexRisk V
- 18:11Pipeline Framework
- 19:22Program Counter
- 20:54Branch Management
- 21:38Practical Example
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