Pyha: Python overlay for OOP-VHDL
summary
Pyha converts object‑oriented Python straight into synthesizable VHDL by turning Python records into VHDL records/registers and translating the clock‑cycle body line-by-line Python→VHDL. It provides a cycle-accurate simulator that is debuggable in Python, supports model vs. RTL vs. Quartus netlist simulations, and wires into a pytest + cocotb test flow. Works on real FPGA flows (with occasional BRAM/program hacks), preserves signal names for tracing, and shows only small quantization differences versus floating‑point models.
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chapters (7)
- 0:00Start
- 1:20What Does It Mean To Be Object-Oriented
- 3:48Constructor
- 4:38Main Function
- 11:00Debuggable Simulator
- 14:21Debugging
- 17:01Future
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