Practical aspects of using the Open Source SCR1 core
summary
SCR1 is an open‑source MCU‑class RISC‑V core (released under the Solderpad Hardware License) that implements RV32I/RV32E with optional M and C extensions, ships with verification collateral and SDKs, and is written in roughly 10,000 lines of SystemVerilog with ~30 configuration options. Tooling includes simulation scripts, Verilator and riscv‑gcc toolchain support, and FPGA reference designs. Over ~16 months it appears in about 20+ commercial and research projects with no serious design bugs reported; several tape‑outs are underway, while no public full physical implementation data is available.
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chapters (10)
- 0:00Introduction
- 0:20Outline
- 0:44Company Introduction
- 2:10What is SCR1
- 5:34Core design
- 6:43Usage
- 8:56SDK
- 9:51Education
- 10:58Summary
- 12:00Questions
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