Extending RISC-V with SCAIE-V
summary
SCAIE-V (demo named Sky 5) generates RTL to plug custom instructions into multiple RISC‑V cores (PicoRV32, VexRiscv, CVA5, CVA6), supports register/PC/memory access and custom registers, and is taped out in 22 nm. Three execution modes—tightly‑coupled, semi‑coupled and decoupled—plus a background demon mode let short and variable‑latency kernels trade area/frequency for latency; a sqrt ISX shows much higher area/freq in semi‑coupled versus decoupled, while app‑class cores incur single‑digit overheads.
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chapters (9)
- 0:00Introducing SCAIE-V and Sky 5
- 1:45Generalized interface importance
- 3:32Generator-based interface design
- 4:37Execution modes in Sky 5
- 7:29Demon-type mode and use cases
- 7:52Evaluation results and overhead
- 8:56Portability and supported cores
- 9:19Current work and future plans
- 9:39Q&A
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