Wildcat: Educational RISC-V Microprocessors

on YouTube ↗14m

" summary

An open-source RISC-V core implemented in Scala/Chisel shows concrete measurements: three-stage pipeline runs faster and uses fewer FPGA resources than four- or five-stage versions on Intel and AMD Xilinx FPGAs and in a SkyWater130 ASIC synthesis, because the wide forwarding multiplexer critical path in longer pipelines limits fmax. A single-cycle prototype even synthesizes to ~7 MHz on an FPGA; a tiny ASIC tapeout (~0.22 mm², register file ~55% of core area) boots a hardcoded hello world LED.

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" chapters (8)

1. 0:00Motivation for Wildcat
2. 0:42Analysis of existing cores
3. 1:41Wildcat design philosophy
4. 2:38Critique of five-stage design
5. 5:06Advantages of three stages
6. 6:15Synthesis and results
7. 9:00Project summary and origins
8. 10:21Q&A and discussion

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