RISC-V: Hardcore/Softcore Co-Simulation Environment with Cycle-Accurate Rollback

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" summary

Realtime co-simulation compares a Verilog RISC‑V core with a C softcore via a C++ checker that flags mismatches on resource‑access notifications, enabling immediate detection of hardware/software divergence. It implements a tri‑granular verification model (transaction/stage/cycle), records PC/register/memory state, and offers 64‑cycle compressed temporal rollback for time‑travel debugging and exact replay. Failures spawn unit/integration replay and fault‑state test generation; current codebase is a proof‑of‑concept tightly coupled to the presenter’s RISC‑V implementation.

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" chapters (7)

1. 0:00RISC-V co-simulation intro
2. 1:02Core objectives and features
3. 2:30State recording and rollback
4. 4:40Time travel debugging
5. 6:27RISC-V instruction library
6. 9:23Live demo and conclusion
7. 9:52Q&A

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