CORE-V Verification Test Bench – Commercial Qualit...
summary
Open-source step-and-compare UVM/SystemVerilog test bench runs instruction-by-instruction retire checks of PC, GPRs and CSRs against an Imperas RISC‑V Golden Reference Model (wrapped via SystemVerilog DPI) while using the Google random instruction generator and GCC toolchain. The environment lives on the Metrics cloud EDA platform with pay‑per‑use simulator instances, automatic coverage merging, test ranking and CI-triggered nightly regressions. It targets the 32‑bit four‑stage CORE‑V (CBE4) core and aims to deliver industry‑quality verification ready for high‑volume SoC use.
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chapters (7)
- 0:00Introduction to CORE-V
- 1:25Open Hardware Group overview
- 3:30Verification task group focus
- 6:21CORE-V test bench overview
- 6:43Imperas reference model role
- 13:42Metrics cloud platform use
- 22:55Q&A session
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