BM-310 Small and Efficient MCU Core
summary
A two-stage, single-issue RISC-V core with selectable extensions (M C A F B and C), four pipeline configurations trading area for clock and IPC, and claimed real silicon runs from 450–700 MHz and measures 19% faster than Cortex‑M4 in a published IoT benchmark; memory uses TCMA/TCMB tightly coupled banks plus an optional n‑way instruction cache with prefetch and priority-chunk fetch; interrupt options range from simple local lines to a CLIC with up to 4080 user interrupts and 256 priority levels; JTAG/C‑JTAG, instruction trace, WFI power gating, FPGA bitstreams and source-eval licensing are available.
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chapters (10)
- 0:00Introduction and overview
- 1:28BM-310 core features
- 3:58Pipeline configurations and performance
- 9:03Memory subsystem and caches
- 11:10Power management and security
- 13:40Debugging and development tools
- 15:04Interrupt handling mechanisms
- 18:37Multi-core and system infrastructure
- 20:03IP delivery and evaluation
- 22:15Licensing and next steps
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