An Introduction to RISC-V Vector Programming with C Intrinsics
summary
Overview of the RISC-V vector ISA and a C intrinsics proposal on GitHub with concrete examples using an Andes NX27V core and an LLVM-based toolchain. Demonstrates vsetvl/vl to select runtime vector length, vle/vse loads/stores, masking and LMUL widening (e.g., LMUL=2), a vectorized loop that returns VL for leftovers, and compiler actions that emit v-instructions and remove redundant vsetvl. Claims conformance to vector spec v0.9 and working codegen on NX27V.
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chapters (6)
- 0:00Introduction to Vector Tool
- 0:21Vector Data and Mask Types
- 3:41Intrinsic Functions & Overloads
- 6:09Masked Operations
- 6:57Vectorization Example
- 9:09Compiler Support & Conclusion
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