Keynote: The Open Source Hardware Roadmap
summary
CHIPS Alliance hosts concrete open hardware work: Verilator 11x faster claims and an ongoing system Verilog upgrade, OpenROAD rtl-to-gds delivers a working single‑button RTL→GDS flow tested with SweRV, and AIB 2.0 doubles I/O density and data rate while lowering voltages. Projects ship usable IP: SweRV EH2 is a dual‑threaded high‑perf embedded core, EL2 is a tiny 4‑stage core running up to 600 MHz in 16 nm, and Omni-Extend demos show coherent memory across two‑ and four‑RISC‑V nodes.
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chapters (6)
- 0:00Introduction to Chips Alliance
- 0:33Goals and design challenges
- 2:38Work groups and key projects
- 4:04Toolchain advancements
- 6:22Specifications and demonstrations
- 8:56Summary and future outlook
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