Zvonimir Z Bandić
where else to find them
no profile links on file
what they talk about
all 4 in the filters
where they keep going back
- ORConf2 editions2018–2019
all 4 in the filters
on a stage with
- Cyril Guyotonce
- Dejan Vuciniconce
- Filip Blagojevićonce
all 7 in the filters
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Keynote: The Open Source Hardware Roadmap | RISC-V Global Forum 2020 | 2020-09-03 |
CHIPS Alliance hosts concrete open hardware work: Verilator 11x faster claims and an ongoing system Verilog upgrade, OpenROAD rtl-to-gds delivers a working… | ||
| RISC V and Chips Alliance Address new Compute Requirements | RISC-V Summit 2019 | 2019-12-09 |
CHIPS Alliance organizes shared open-source IP and tools to cut SOC design cost by avoiding duplicate RISC‑V core work, hosting concrete projects: a VH1… | ||
| SweRV Cores Roadmap | RISC-V Summit 2019 | 2019-12-09 |
Roadmap describes two SweRV second‑generation cores: a tiny L2 aimed at minimal area and one‑IPC from local memories — measured at 0.023 mm² (TSMC 16nm) with… | ||
| Chips Alliance Project | ORConf 2019 | 2019-09-27 |
CHIPS Alliance organizes corporate-backed open hardware projects under Apache-2.0 license and a Linux Foundation home, with membership tiers (platinum ~$25k… | ||
| OmniXtend cache coherence protocol for datacenter CPUs | ORConf 2019 | 2019-09-27 |
OmniXtend maps TileLink over Ethernet into 802.3 L1 frames and runs a P4 data plane on a Barefoot/Tofino switch, with the OmniXtend spec and P4 code… | ||
| RISC-V CPU Project in Western Digital | ORConf 2018 | 2018-09-21 |
Western Digital develops a RISC-V core ECHX1 as a 2-way superscalar 9-stage pipeline implemented in TSMC 28 nm reaching ~970 MHz (target 1 GHz) and occupying… | ||
| Priority IO Scheduling in the Cloud | HotCloud '13 | 2013-06-25 |
Implements priority-based (PBS) IO scheduling by passing priorities from HDFS through a user-level JNI + SG_IO path into the Linux kernel and SATA device using… | ||
| nothing matches | ||