OmniXtend cache coherence protocol for datacenter CPUs
summary
OmniXtend maps TileLink over Ethernet into 802.3 L1 frames and runs a P4 data plane on a Barefoot/Tofino switch, with the OmniXtend spec and P4 code open-sourced. A backplane reference PCB is taped out for ~2,000 units and the prototype ties two 4‑core RISC‑V nodes into an 8‑core cluster via the OmniXtend switch. FPGA prototypes measure about 2 µs round‑trip latency (50 MHz FPGAs) and target a few hundred nanoseconds on ASIC; the TileLink serializer currently uses a SiFive IP.
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chapters (13)
- 0:00Introduction
- 0:27Agenda
- 2:12datacenter CPU vision
- 7:02vision
- 7:29reference design
- 9:03other standards
- 11:44OmniXtend
- 12:20Barefoot Networks
- 13:17NanoSwitch
- 13:50Cache Coherence
- 15:56Demo
- 16:22FPGA performance
- 18:23Conclusions
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