netlist-paths: A command line tool for querying paths in Verilog
summary
Command-line tool netlist-paths uses a modified Verilator to produce a flattened netlist from Verilog and lets users query exact paths by specifying start end and through points. It prints full intermediate net names so timing-report paths map back to RTL, can list all paths into a register or show full logic cones, and handles large designs (author mentions a ~700 MB netlist from an Nvidia example). Currently ties blocks/processes but not variable-level linking; source on GitHub.
AI-written summary · about
chapters (5)
related talks
33mThe nextpnr FOSS FPGA place-and-route tool
18mGiving Students A Byte of Open-Source: Advancing Hardware Education
20mOpen-Source FPGAs: Tools, Flows, and Visualization
28mBPF Verifier Visualizer
20mNetTLP: A Development Platform for PCIe devices in Software Interacting with Hardware
11mnajaeada - Getting closer to an industrial grade ECO solution with an open source stack
56mProgramming FPGAs - The Open Source Way
01h 12mTutorial