OpenRISC update
summary
Update covers concrete progress: GCC port completes, glibc port is underway with several bug fixes (one-line PLT write fix, GOT register change from r9), and QEMU support lands upstream. New Marocchino CPU implements Tomasulo-style out-of-order execution with tiny reservation stations (two entries) and 64-bit via register pairs but runs slower than the pipelined cappuccino core. Spec 1.3 adds the ADRP instruction and removes hardware FP remainder; LibreCores CI now runs synthesis and reports Lattice resource usage.
AI-written summary · about
chapters (6)
- 0:00Start
- 1:03What Is Open Risk
- 3:32Spec Update
- 5:18Continuous Integration
- 9:46Performance
- 14:54G Lib C Porting
