Synthesize HDL to 7400 logic
summary
Workflow uses Yosys to synthesize HDL down to 74‑series logic via a Liberty file, exports JSON, and a script generates a KiCad netlist for place‑and‑route and PCB ordering. A simple PWM board is built and worked first try; full CPU cores found online need 300–500 chips, so goal is a sub‑100‑chip tiny CPU. ALU is open source HDL and is partially formally verified with Symbiotic EDA.
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