Continuous VHDL inspection with opensource software
summary
CNES-developed VHDLTool centralizes a company-editable XML rule set to PDF, builds a rulechecker on top of Zamiacad/Sameiacad, and ships a Sonarqube-rulechecker plugin plus a scanner/server model that runs locally or via commit hooks. The project currently implements 26 of 100 rules, pulls coverage from VHDL Coverage or ModelSim/GCOV, and flags concrete issues like clock reassignment that break simulation semantics rather than vague style suggestions.
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chapters (9)
- 0:00Introduction
- 2:11The journey
- 12:14Quality code management
- 12:59Simulation
- 13:32Clock Reassignment
- 14:35Presentation
- 15:42System
- 17:29Questions
- 21:46Collaboration
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