ORConf 2019
| title | author | length |
|---|---|---|
| Welcome to ORConf 2019 | Olof Kindgren | 08m |
Welcome note that traces open‑source silicon from 20 years since 1999 through a 2002 commercial spike (Flextronics), a 2008 revival (ORSoC buying OpenRISC)… | ||
| About FOSSi Foundation | Stefan Wallentowitz | 11m |
Foundation is a UK Community Interest Company since 2015 with an asset lock, run by seven volunteer directors and committees handling licensing, stewardship… | ||
| Chips Alliance Project | Zvonimir Z Bandić | 43m |
CHIPS Alliance organizes corporate-backed open hardware projects under Apache-2.0 license and a Linux Foundation home, with membership tiers (platinum ~$25k… | ||
| Open Hardware Licensing | Andrew Katz, Javier Serrano | 47m |
CERN OHL v2 is a three‑variant license family: P (permissive), L (weak reciprocal) and S (strong reciprocal); copyleft obligations apply only up to a defined… | ||
| The Momentum and Opportunity of Custom, Open Source Processing | Calista Redmond | 22m |
RISC-V claims that open source cores cut development cost, risk, and time to market so companies can build thousand‑kind custom processors tuned for AI, IoT… | ||
| Microwatt - A simple Open POWER soft processor | Anton Blanchard | 17m |
Microwatt is a tiny Open POWER soft core published on GitHub in late August that implements a ~100‑instruction fixed‑point subset of the POWER ISA, written in… | ||
| Open-source model checkers: Ready for the industry? | Sergey Smolov | 22m |
Open source penetrates the microelectronics design, making hardware development more accessible. To leverage this effect, one needs open CAD tools, including… | ||
| Open Source Formal Verification in VHDL | Pepijn de Vos | 13m |
GHDL now synthesizes VHDL into Yosys via a GHDL→Yosys plugin and supports PSL in VHDL‑2008 so SymbiYosys can run SMT solvers on designs. A hand‑built… | ||
| Continuous VHDL inspection with opensource software | Florent Manni | 24m |
CNES-developed VHDLTool centralizes a company-editable XML rule set to PDF, builds a rulechecker on top of Zamiacad/Sameiacad, and ships a… | ||
| What's new in LibreCores CI? | Oleg Nenashev | 28m |
Project started in 2016 and now offers reusable Docker images for EDA tools (cocotb, Verilator, RISC‑V toolchain) on Docker Hub, a Jenkins pipeline library for… | ||
| ASICone, from Verilog to GDSII with open source tools | Luis E. Rueda G. | 44m |
ASICone attempts a full tape-out of a RISC‑V 32‑bit microcontroller on X‑Fab 180nm CMOS using only open‑source tools. The team actually generates standard… | ||
| A Unified Debug Server for Deeply Embedded Systems and GDB/LLDB | Simon Cook | 16m |
An open source debug server presents a simple abstraction over the GDB/LLDB remote serial protocol, mapping packets to thin callbacks for register/memory… | ||
| Open Source Processor IP for High Volume SoCs | Rick O'Connor | 29m |
A nonprofit organization organizes commercial-quality open-source RISC-V cores as the CORE-V family and moves the PULP platform Rocket and Ariane… | ||
| News from cocotb land | Philipp Wagner | 31m |
cocotb now ships as a pip package so you can pip install cocotb and run Python-driven RTL tests; the project grew by 20,000 lines between long gaps and moves… | ||
| Renode coming to a cloud near you | Michael Gielda | 29m |
Renode 1.8 adds multi-core GDB support, Verilator co-simulation and an Etherbone FPGA bridge so most of a SoC runs fast in the simulator while one IP runs in… | ||
| Embench 0.5: A Free Benchmark Suite for IoT | Jeremy Bennet | 24m |
Embench 0.5 is a free suite of 19 real programs (targeting ≤64KiB code ≤16KiB data) that reports a single performance score as the geometric mean and geometric… | ||
| TerosHDL: an open source IDE for FPGA developers | Ismael Pérez, Carlos Alberto, Alfredo Sáez | 21m |
TerosHDL 2.0 is an open source IDE layer (currently an Atom plugin) that integrates ghdl, VUnit and adds Verilator, Icarus, cocotb and Edalize support, plus a… | ||
| OmniXtend cache coherence protocol for datacenter CPUs | Zvonimir Z Bandić | 24m |
OmniXtend maps TileLink over Ethernet into 802.3 L1 frames and runs a P4 data plane on a Barefoot/Tofino switch, with the OmniXtend spec and P4 code… | ||
| The State of Chips4Makers, an ASIC Service for Makers and Hobbyists | Staf Verhaegen | 21m |
Chips4Makers describes a low-cost ASIC service for makers using open-source toolflows—notably the Coriolis flow—plus foundry rule integration and retro-MCU IP… | ||
| OpenRISC update | Stafford Horne | 22m |
Update covers concrete progress: GCC port completes, glibc port is underway with several bug fixes (one-line PLT write fix, GOT register change from r9), and… | ||
| VPR device models generation from Verilog with V2X | Karol Gugala | 19m |
V2X converts Verilog models into VPR architecture XML (model and pb_type) by running Yosys to JSON then Python generators that emit PB type and model files… | ||
| Status of Xilinx Artix 7 support in Symbiflow | Tim Ansell | 03m |
As of December 2018 Series 7 bitstream support via Project X-Ray reaches the point where simple IoT designs are runnable and the codebase can fully describe a… | ||
| Improving VPR I/O | Fahrican Koşar | 03m |
Work on verilog-to-routing's P&R tool VPR makes the arch and routing file I/O faster file parsing and closes correctness gaps in how architecture and routing… | ||
| SystemVerilog compatibility Test-Suite | Henner Zeller | 03m |
An open-source SystemVerilog test suite systematically exercises the standard with hundreds of compact test cases and runs each case across multiple simulators… | ||
| netlist-paths: A command line tool for querying paths in Verilog | Jamie Hanlon | 03m |
Command-line tool netlist-paths uses a modified Verilator to produce a flattened netlist from Verilog and lets users query exact paths by specifying start end… | ||
| Open Source SCR1 core | Ekaterina Berezina | 03m |
SCR1 is an open-source MCU-class RISC-V core that ships on GitHub with configurable RTL, QuickStart guides, tests and simulation scripts and an SDK repository… | ||
| RISC-V without a Register File | David Hossack | 03m |
Removes the conventional RISC-V register file and maps registers into memory so the first bytes act like zero-page style register access; the prototype is a… | ||
| Visions of the future (Clash 1.0) | Christiaan Baaij | 03m |
Clash 1.0 compiles high-level Haskell into VHDL and SystemVerilog and now implements configurable clock domains with selectable rising or falling edges… | ||
| Synthesize HDL to 7400 logic | Pepijn de Vos | 03m |
Workflow uses Yosys to synthesize HDL down to 74‑series logic via a Liberty file, exports JSON, and a script generates a KiCad netlist for place‑and‑route and… | ||
| What's new in Chisel | Jack Koenig | 03m |
Chisel 3.2 reaches second release candidate with a breaking upgrade from 3.1 and a bumped Rocket Chip branch available for testing. Key additions include… | ||
| Reusing HW Components with DUH Flow | Aliaksei Chapyzhenka | 23m |
DUH is an open-source JSON-based data format for describing reusable hardware IP: ports, bus interfaces, memory maps, registers, generator parameters, clocks… | ||
| Onboarding Verilog Peripherals to Rocket Chip | Jack Koenig | 19m |
Rocket Chip integration workflow that automates Verilog IP onboarding using a machine-readable DO manifest plus repo orchestration with wit repo manager and… | ||
| Unleashing the Potential of Cloud FPGAs | Ákos Hadnagy | 17m |
Having FPGAs available in the data center presents enormous potential for new and exciting compute models. But, for this emerging ecosystem to thrive, we need… | ||
| Taking nextpnr to the next level! | David Shah | 17m |
nextpnr becomes a production-ready place-and-route for Lattice ECP5 with 29 contributors since May 2018, replacing simulated-annealing placement with the HeAP… | ||
| Open Source computer architecture research at the BSC | Guillem Cabo | 18m |
Barcelona Supercomputing Center produces a first silicon RISC‑V ASIC: a 5‑core RV64 microprocessor, five‑stage pipeline, fully in Verilog, integrated into a… | ||
| BlackEdge Based FPGA-OSH | Alan J. Wood | 19m |
A new hardware standard called BlackEdge standard defines two 50‑pin headers that expose 48 digital I/Os, 16 analog signals, SPI, I2C, UART and eight spare… | ||
| DPI protected Verilog instead of encryption | Todd Strader | 24m |
Encrypted Verilog is weak (see referenced ACM CCS paper) so the project compiles secret RTL with Verilator into a DPI-accessible shared object, shipping the… | ||
| Formally Verifying AXI Interfaces | Dan Gisselquist | 25m |
A compact property set for AXI and AXI-lite is implemented and run with SymbiYosys against many open-source and vendor demo cores, revealing concrete failures… | ||
| One simulator to rule them all, and on an infrastructure run them | Benjamin Barrois | 23m |
Hiventive runs multiple existing simulators (QEMU, gem5, SystemC) together under a coordinator called sim guru and thin sim disciple wrappers to present a… | ||
| What has PULP team been working on lately | Frank K. Gürkaynak | 25m |
PULP reports 36 ASICs taped out since 2013 (~6/year) and publishes proven RTL and software on GitHub under the Solderpad license; some analog IP and… | ||
| RudolV: from the RISC-V SoftCPU Contest to a Timing-Predictable Core | Jörg Mische | 22m |
RudolV is a 5-stage in-order RISC-V CPU core designed for timing predictability by avoiding speculative features such as out-of-order execution, dynamic branch… | ||
| On a Quest for the Ideal HDL(s) for Makers and Hobbyists | Staf Verhaegen | 20m |
Discusses how common RTL HDLs (Verilog/VHDL-style) force implicit clock/reset models and confusing blocking vs non‑blocking semantics, which break small maker… | ||
| nothing matches | ||