Rick O'Connor
where else to find them
what they talk about
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where they keep going back
- embedded world2 editions2019–2022
all 10 in the filters
on a stage with
- Drew Barbier2×
- Aimee Suttononce
- Alexander Kozlovonce
all 15 in the filters
who talks about the same things
- Massimiliano Giacometti2 talks
- Calista Redmond37 talks
- Olof Kindgren14 talks
- Stephano Cetola6 talks
- Hugh Blemings8 talks
- Karol Gugala12 talks
| title | conference | date |
|---|---|---|
| Open-Source HW Commercial Adoption: Lessons Learned | RISC-V Summit North America 2023 | 2023-11-06 |
CORE-V family is SystemVerilog IP with auditable, pre-silicon functional verification and open-source testbenches that run on Cadence Synopsys and Siemens… | ||
| Commercial Adoption of CORE-V Open-Source RISC-V Cores - Lessons Learned | RISC-V Summit Europe 2023 | 2023-06-05 |
OpenHW’s CORE‑V family provides SystemVerilog RISC‑V cores with a UVM verification bench that runs on commercial EDA simulators and has 54 GitHub project… | ||
| Open-Source HW Commercial Adoption: Lessons Learned | EclipseCon 2022 | 2022-10-24 |
OpenHW Group describes a pragmatic path to commercial open-source silicon: a permissive solderpad license on top of Apache, a public UVM-based verification… | ||
| OpenHW CORE-V MCU DevKit for Cloud Connected IoT | embedded world 2022 | 2022-06-21 |
Demonstration shows an open-source RISC‑V CV32E40P core instantiated in a CORE‑V MCU DevKit (emulated on FPGA, 22FDX tapeout pending, silicon expected late… | ||
| CORE-V Verification Test Bench – Commercial Qualit... | RISC-V Global Forum 2020 | 2020-09-03 |
Open-source step-and-compare UVM/SystemVerilog test bench runs instruction-by-instruction retire checks of PC, GPRs and CSRs against an Imperas RISC‑V Golden… | ||
| Open Source Processor IP for High Volume Production SoCs CORE V Family | RISC-V Summit 2019 | 2019-12-09 |
OpenHW Group commits to produce production-grade CORE-V cores and tape out a submicron SoC by end of 2020 using NXP’s donated i.MX as the non‑open peripheral… | ||
| Processor IP Showcase | RISC-V Summit 2019 | 2019-12-09 |
Session collates multiple RISC-V IP offers and concrete claims: market research projects RISC‑V ecosystem hitting about $1B with ~50% CAGR; Andes reports >180… | ||
| Open Source Processor IP for High Volume SoCs | ORConf 2019 | 2019-09-27 |
A nonprofit organization organizes commercial-quality open-source RISC-V cores as the CORE-V family and moves the PULP platform Rocket and Ariane… | ||
| RISC-V Adoption in open source implementations, a personal perspective | Week of Open Source Hardware 2019 | 2019-06-13 |
An initiative forms to take ETH Zurich cores (the Ariane and Rocket cores) out of university repos and into industry by providing commercial-grade… | ||
| Andes Technology | Embedded World 2019 | 2019-02-26 |
Announces the n22 microcontroller core, a minimal RISC‑V core aimed at deeply embedded, IoT and wearable applications claiming low area, low power and "good… | ||
| CloudBEAR | Embedded World 2019 | 2019-02-26 |
CloudBEAR shows a working RISC-V Linux core on FPGA that hosts a website and remotely controls an IoT device, plus a tiny microcontroller and an Eclipse-based… | ||
| Imperas | Embedded World 2019 | 2019-02-26 |
Imperas provides instruction-accurate virtual platforms that model RISC‑V cores and let teams add peripheral and SoC models, run the actual compiled binaries… | ||
| SiFive | Embedded World 2019 | 2019-02-26 |
SiFive offers RISC‑V processor IP and custom ASIC builds plus a web‑based configurator called SiFive 4 Designer that is effectively a core generator for tuning… | ||
| UltraSoC | Embedded World 2019 | 2019-02-26 |
Demo shows an FPGA with two ARM cores and a RISC‑V core running UltraSoC live monitoring and a new chip analytics suite that uses ML-based analytics to surface… | ||
| GreenWaves Technologies | Embedded World 2019 | 2019-02-26 |
GAP8 is a low power RISC-V MCU built on the PULP RISC-V core with five years of tested IP and a toolchain that reuses existing RISC-V partners so engineering… | ||
| Syntacore | Embedded World 2019 | 2019-02-26 |
Syntacore announces four new 64-bit cores and offers turnkey RTL customization plus ISO design services tailored to workload and toolchain needs. Demos show a… | ||
| RISC-V Foundation Presentation | Embedded World 2019 | 2019-02-26 |
RISC‑V presents a free, open ISA governed by a nonprofit foundation (incorporated August 2015) with over 235 members and an ecosystem that grew to ≈1,150… | ||
| RISC-V ISA & Foundation Overview | RISC-V Workshop Chennai 2018 | 2018-07-18 |
RISC‑V claims a simple, modular ISA that scales from teaching to production: the base RV32I base <50 instructions plus standard extensions like M, A, F, D and… | ||
| RISC-V Workshop Chennai Conclusion | RISC-V Workshop Chennai 2018 | 2018-07-18 |
Presentation by Rick O’Connor at RISC-V Foundation on July 19, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian Institute of Technology Madras in… | ||
| 7th RISC V Foundation Update And Workshop Introduction | 7th RISC-V Workshop 2017 | 2017-11-28 |
Conference reports 498 registered attendees from 138 companies and 35 universities, with venues repeatedly selling out and 48 talks crammed into 12‑ and… | ||
| 7th RISC V Workshop Wrap | 7th RISC-V Workshop 2017 | 2017-11-28 |
All slides and videos get posted on riscv.org next week, raw footage undergoes post-processing first; members find a PDF agenda for tomorrow’s Board, Technical… | ||
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