~/talks

Aimee Sutton

where else to find them

no profile links on file

what they talk about

where they keep going back

RISC-V Summit North America2 editions2023–2024

on a stage with

all 5 in the filters

who talks about the same things

nobody close enough yet

title	conference	date
Combined Dynamic and Formal Verification Approach to Processor Verification	RISC-V Summit North America 2024	2024-10-22
Combines Synopsys tools and workflows to find more bugs faster: unit-level formal using VC Formal and assertion IP (AIP) exhaustively checks buffers, decoder… Talk on
Demo: Open Standards and Verification Methodology for RISC-V Processors	RISC-V Summit North America 2023	2023-11-06
Imperas DV is a ready-to-run RISC-V processor verification stack: an instruction-accurate reference model plus verification IP that hooks to testbenches via… Talk on
Challenges in CPU DV: Why "It Boots Linux" Is Not Verification	RISC-V Summit North America 2023	2023-11-06
CVWally is a configurable RISC‑V core that can boot Linux but that confidence proves hollow: using an RVVI tracer, Imperas DV, and RISC‑V DV random instruction… Talk on
Tutorial: Choosing Appropriate Verification Techniques for Desired RISC...	RISC-V Summit 2022	2022-12-13
A structured verification flow centers on an Imperas reference model plus a standardized RISC-V Verification Interface (RVVI) with rvvi trace and an rvvi API… Talk on
Demo: Introduction to RISC-V Verification with the Open Standard RVVI (RISC-V Verifi...	RISC-V Summit 2022	2022-12-13
RISC‑V processor verification consumes around 50% of SoC development cost, and RVVI proposes a concrete, open standard with three parts: RVVI Trace (a… Talk on
CORE-V Verification Test Bench – Commercial Qualit...	RISC-V Global Forum 2020	2020-09-03
Open-source step-and-compare UVM/SystemVerilog test bench runs instruction-by-instruction retire checks of PC, GPRs and CSRs against an Imperas RISC‑V Golden… Talk on
nothing matches

-- 6 of 6 talks indexed --