Lee Moore
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what they talk about
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where they keep going back
- RISC-V Summit2 editions2019–2022
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| title | conference | date |
|---|---|---|
| Tutorial: Choosing Appropriate Verification Techniques for Desired RISC... | RISC-V Summit 2022 | 2022-12-13 |
A structured verification flow centers on an Imperas reference model plus a standardized RISC-V Verification Interface (RVVI) with rvvi trace and an rvvi API… | ||
| The New Verification Ecosystem that Supports RISC-V Verification fo... | RISC-V Summit 2022 | 2022-12-13 |
A configurable imperas DV processor model acts as a cycle-accurate reference for RTL checks while Breker’s test-suite synthesis generates run-ready tests from… | ||
| Lightning Talk: Software Development for ML and RISC-V Vector Acceler... | RISC-V Forum: Vector & Machine Learning 2021 | 2021-09-15 |
Imperas provides fast virtual platforms that boot Linux in ~15 seconds and simulate heterogeneous Arm + RISC-V arrays to develop software long before silicon… | ||
| Lightning Talk: Design Verification with Step-and-Compare for RISC-V... | RISC-V Forum: Vector & Machine Learning 2021 | 2021-09-15 |
Uses an asynchronous lockstep compare against an architectural “envelope” model that covers drafts and extensions, exporting GPRs FPRs CSRs and the vector… | ||
| Verifying All the Flexibility of RISC-V within SoC DV Test Plans | RISC-V Global Forum 2020 | 2020-09-03 |
Updates to the RISC-V compliance suite use the riscvOVPsim reference model and integrate with open instruction generators (Google ISR) and UVM flows to run… | ||
| RISC V Processor Verification based on Open source Framework | RISC-V Summit 2019 | 2019-12-09 |
Describes an open-source verification flow using Imperas instruction-accurate models plus a RISC-V config YAML to drive simulator, compliance tests and… | ||
| RISC V Verification for Processor Cores and Optional Custom Extensions | RISC-V Summit 2019 | 2019-12-09 |
An open verification flow combines the OVPsim reference model, Google’s UVM stream generator and Metrics cloud RTL simulation to run compliance and DV at… | ||
| RISC-V Virtual Platforms for Early RISC-V Embedded Software Development | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Imperas and Ashling show virtual platforms that let embedded teams start software months before silicon, using a library of over 200 processor models and… | ||
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