RISC V Verification for Processor Cores and Optional Custom Extensions
summary
An open verification flow combines the OVPsim reference model, Google’s UVM stream generator and Metrics cloud RTL simulation to run compliance and DV at scale. Mutation testing flips instruction bits and creates ~15,000 fault runs to prove that coverage actually propagates to the signature. Vector testing currently has ~2,000 tests and estimates >10,000+ vector tests needed. A DPI-embedded reference model enables cycle‑by‑cycle RTL vs ISS compares, and IBEX runs show the flow works.
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chapters (24)
- 0:00Start
- 2:01Reference Simulator
- 2:49Resources
- 4:12Requirements for Verification
- 5:00Compliance Working Group
- 12:04What Is Compliance Trying To Do
- 14:24Code Snippets
- 15:21Static Approach
- 19:09Constraints
- 24:25The Compliance Memory Footprint
- 33:14Mutation Testing
- 37:41Types of Mutation Testing
- 42:48Vector Extension Testing
- 45:13Hardware Design Verification
- 49:40Direct Procedural Interface
- 51:57Instruction Stream Generation
- 52:19Compliance and Verification
- 58:14Randomness
- 1:08:24Live Demo
- 1:08:44Google Uvm Generator
- 1:15:01How Users Interact with Metrics
- 1:18:54Dashboard
- 1:19:50Results Screen
- 1:21:26Coverage Report
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