Richard Ho
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| title | conference | date |
|---|---|---|
| RISC-V Open ISA’s Shock Wave of Processor Innovation Causing Seismic Shift | RISC-V Summit 2019 | 2019-12-09 |
Open RISC‑V implementations drive extensibility that raises verification from compliance checks into full system and security validation: designers report… | ||
| Open Source Verification Platform for RISC V Processors | RISC-V Summit 2019 | 2019-12-09 |
An open-source RISC-V verification platform generates constrained-random instruction streams, produces page tables, trap handlers and traces, and plugs into… | ||
| RISC V Processor Verification based on Open source Framework | RISC-V Summit 2019 | 2019-12-09 |
Describes an open-source verification flow using Imperas instruction-accurate models plus a RISC-V config YAML to drive simulator, compliance tests and… | ||
| RISC V Verification for Processor Cores and Optional Custom Extensions | RISC-V Summit 2019 | 2019-12-09 |
An open verification flow combines the OVPsim reference model, Google’s UVM stream generator and Metrics cloud RTL simulation to run compliance and DV at… | ||
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