Formal Methods for Hardware Software Integration on RISC V Embedded Systems
summary
A complete digital stack — pipeline RISC‑V CPU plus software image — runs on an FPGA implementation connected to an Ethernet controller and a power switch to toggle a light via UDP packets; the system is written in Bedrock2 and verified in Coq. Specifications are regular‑expression logs and parameterized interfaces; proofs include compiler correctness and invariant preservation. The toolchain exhaustively verifies behavior for all inputs, parameters and steps, the Coq theorem proves the observed log matches the regex, and the device behaves as specified on hardware.
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chapters (8)
- 0:00The role of interfaces
- 2:28Prototype system overview
- 4:47Specifying system behavior
- 7:48Formal verification with Coq
- 10:14Proof mechanics and invariants
- 12:56Parameterizing specifications
- 15:12Engineering tradeoffs
- 17:26Context and conclusion
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