Introduction to RISC-V Processor Verification

on YouTube ↗13m

" summary

Covers five simulation-based DV flows from simple post-simulation trace compare to asynchronous co-simulation step-and-compare and claims the latter handles interrupts, multi-core and out-of-order pipelines. Uses Imperas ISS/OVPsim+ and Imperas DV verification IP with synchronization, scoreboarding and instruction coverage; connects via the RVBI/RVVI standard. Mentions Google’s RISC-V DV instruction generator, 250+ reference-model configuration parameters, early pilots with Open Hardware Group and Nvidia Mellanox, and says the toolset is already used to support customer tapeouts.

AI-written summary · about

" chapters (6)

1. 0:00Introduction
2. 1:00Imperas Background
3. 3:16Why RISCV
4. 5:08Challenges
5. 6:44DV Methodology
6. 9:31Imperas DV

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