SiFive Intelligence X280

on YouTube ↗13m

" summary

Update to the SiFive Intelligence X280 adds a VCIX vector coprocessor interface that maps vector registers into the instruction stream so custom accelerators read and write vectors without memory‑mapped transfers, cutting bus traffic and power. Vector engine supports up to 512‑bit ALUs and SiFive Intelligence Extensions including bfloat16. Multi‑cluster scaling now reaches 16 cores (four clusters of four) with a larger coherent last‑level cache and World guard per‑transaction security markers for fine‑grained isolation.

AI-written summary · about

" chapters (6)

1. 0:00Introduction and overview
2. 1:47Sci-Fi product families
3. 3:54X280 22g1 update
4. 6:43Vector co-processor interface
5. 8:52Multi-core and security
6. 11:23Roadmap and future plans

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