Keynote: Taking RISC-V Intelligence Everywhere
Talkat RISC-V Summit North America 2023 · on Wednesday, 2023-11-08· at 09:55· Mission City Ballroom B2 - B5·
summary
RISC-V is shown running from tiny MCUs to datacenter AI with concrete hardware and numbers: a 64-PE array design pairs scalar cores and Vector processors (based on NX27V) and beats competitors on low/medium LMs; photonic coprocessors combine with RISC-V vectors; an SRAM compute tile family claims 256 TOPS in a format, while a 4-cluster chip delivers 200+ TOPS per chip and a MX200 design uses 64k MAC engines for ~30 TOPS. Custom RVV-like extensions yield 1.7–18x speedups on softmax, GELU, matmul and conv; a D25F 100 MHz endpoint shows >50% voice-speedup with P-extension. Tooling includes auto-vectorizing compiler, pruning/quantization and TVM/TensorRT export.
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chapters (10)
- 0:00Introduction to RISC-V AI progress
- 1:05Open-source models driving edge AI
- 2:08RISC-V AI support across workloads
- 3:13RISC-V extensions for AI acceleration
- 3:34AI accelerator examples with RISC-V
- 7:29RISC-V processors for voice AI
- 8:13Andes Technology RISC-V portfolio
- 9:18Custom vector instructions for AI
- 10:44Andes AI solution stack
- 12:07Collaboration for RISC-V AI everywhere
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